1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit (IC), and more particularly to a method of fabricating a metal-oxide-semiconductor (MOS) transistor with an aluminum gate instead of conventional polysilicon gate.
2. Description of the Related Art
MOS transistor is the most important elementary electric device for the vary large scale integration (VLSI) technique at present. It basically consists of stacked thin films of metal, oxide and semiconductor. Silicon is the major semiconductor source for the MOS transistor now. The oxide thin film is made from silicon oxide. As to the metal thin film, though aluminum is widely used for semiconductor devices, some drawbacks, such as difficulties in etching aluminum gate electrode during patterning and problems caused by backend thermal processes after forming aluminum gate electrode, makes the use of aluminum as the metal thin film improper. Moreover, the other metal materials are not used for the metal thin film of MOS transistor either since they mostly suffer from the problems of poor adhesive force with the silicon oxide thin film. Polysilicon, having superior adhesive force with the silicon oxide layer and compatible with the present process, is now the most commonly used material for the gate electrode. However, the problem of high resistance, even processed through doping, makes the use of polysilicon gate electrode limited. One of the solutions for overcoming high resistance is to form a metal silicide layer over the polysilicon gate.
Typically, MOS transistors have the following three categories: 1:n-channel MOS transistor(NMOS), 2.p-channel MOS transistor (PMOS) and 3.complementary MOS transistor (CMOS), whereas the NMOS is the most popular. FIG. 1 shows a cross-section of a conventional NMOS. First, an isolation region 102 is formed on the substrate 100 to isolate the adjacent MOS transistors. Next, a gate oxide layer 104 and a polysilicon gate electrode 106 are successively formed on the substrate 100.
Next, source/drain regions are formed to define the channel region of the MOS transistor. Usually, for the new generation of the memory and logic devices, lightly doped drain (LDD) is used to substitute the conventional source/drain structure so that hot carrier effect is prevented. The LDD structure is typically formed by the following steps: implanting low dosage of dopant into the substrate 100 to form lightly doped regions 108, forming spacer 110 around the polysilicon gate electrode 106, then, using the spacer 110 as a mask, implanting high dosage of dopant to form heavily doped regions 112.
To reduce the resistance of the polysilicon gate electrode 106 and the source/drain region 112, metal silicide layers 118 and 120 are formed on the polysilicon gate electrode 106 and source/drain regions 112, using self-aligned silicide technique. Then, after removing the unreacted and remained titanium, the NMOS transistor is completed.
However, as the integration of the IC is increased, the line width of the MOS transistor is reduced to submicron. The above-mentioned conventional process suffers from high gate resistance, gate tunnel leakage and poly gate deplection and therefore the performance of the MOS transistor is reduced.